Continuing reduction of the minimum features produced by semiconductor processes and reduction in the size of the resulting devices has enabled continued improvements in speed, performance, density, and cost per unit function of integrated circuits and systems. As semiconductor process nodes continue to shrink, the various structures also become smaller. Certain features then experience reduced coupling, which has negative performance impact on the non-volatile cells. For example, the erase gate to floating gate coupling is a function of the area of the two structures which are formed separated by one or more dielectric layers. As the cell sizes shrink, the structures shrink and the erase gate to control gate coupling is reduced, which reduces performance.
In a typical “split gate” arrangement for FLASH cells, the erase gate is formed over a common source region between memory two cells each having control gates over floating gate electrodes that are surrounded by dielectric material. The coupling area of the floating gate and the erase gate that is available for coupling during a cell programming cycle is important to the cell performance. As the area for coupling is reduced, the programming cycle performance degrades. This is reflected either in the need for increased potentials on the control gate or in reduced programming speed.
As reliable memory becomes increasingly important for portable devices, such as mobile phones, tablet computers and other battery operated devices, the use of non-volatile memory is increasingly prevalent. Thus, the need for efficiently manufactured, robust and cost effective FLASH memory cells with high performance is increasing.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the illustrative embodiments and are not necessarily drawn to scale.